IEEE

A High Payload Double Secured Video Steganography based on AES Encryption and BCH code

Abstract: Because of advancements in information and communication technologies, the science of encryption has risen to prominence in recent years. This method is designed to conceal hidden text and ...
IEEE

Image Cryptography using AES-256 Algorithm

Abstract: Due to the advancement of technology, information security and user privacy have become a critical issue resulting in the use of various encryption techniques. Especially with the increasing ...
GitHub

Description This project demonstrates the implementation of a Half Adder using Verilog HDL. It performs addition of two single-bit inputs and generates Sum and Carry outputs ...

This project implements a Half Adder using Verilog HDL. A Half Adder is a basic combinational circuit that adds two 1-bit inputs (A, B) and produces two outputs: Sum and Carry. The design is written ...